IEEE802dot3ad portlist is indexed with a dot1dBasePort, cross reference with dot1dBasePortIfIndex
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@@ -64,7 +64,8 @@ sub agg_ports_lag {
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my $dev = shift;
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# TODO: implement partial
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my $ports = $dev->ad_lag_ports;
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my $ports = $dev->ad_lag_ports();
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my $index = $dev->bp_index() || {};
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return {} unless ref {} eq ref $ports and scalar keys %$ports;
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@@ -73,9 +74,18 @@ sub agg_ports_lag {
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my $idx = $m;
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my $portlist = $ports->{$m};
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next unless $portlist;
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# While dot3adAggTable is indexed by ifIndex, the portlist is indexed
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# with a dot1dBasePort, so we need to use dot1dBasePortIfIndex to map to
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# the ifIndex. If we don't have dot1dBasePortIfIndex assume
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# dot1dBasePort = ifIndex
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for ( my $i = 0; $i <= scalar(@$portlist); $i++ ) {
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$ret->{$i+1} = $idx if ( @$portlist[$i] );
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}
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my $ifindex = $i+1;
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if ( exists($index->{$i+1}) and defined($index->{$i+1}) ) {
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$ifindex = $index->{$i+1};
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}
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$ret->{$ifindex} = $idx if ( @$portlist[$i] );
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}
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}
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return $ret;
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