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2 Commits
| Author | SHA1 | Date | |
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5af11cb612 | ||
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aa17e6865c |
@@ -63,6 +63,8 @@ sub agg_ports_ifstack {
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foreach my $idx ( keys %$ifStack ) {
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my ( $higher, $lower ) = split /\./, $idx;
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next if ( $higher == 0 or $lower == 0 );
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next unless exists $ifType->{ $higher } and defined $ifType->{ $higher };
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if ( $ifType->{ $higher } eq 'ieee8023adLag'
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or $ifType->{ $higher } eq 'propMultiplexor' ) {
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$ret->{ $lower } = $higher;
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@@ -153,6 +153,8 @@ sub agg_ports_propvirtual {
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foreach my $idx ( keys %$ifStack ) {
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my ( $higher, $lower ) = split /\./, $idx;
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next if ( $higher == 0 or $lower == 0 );
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next unless exists $ifType->{ $higher } and defined $ifType->{ $higher };
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if ( $ifType->{ $higher } eq 'propVirtual' ) {
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# lower needs also to be configured in pagpEthcOperationMode
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@@ -873,8 +873,12 @@ sub agg_ports {
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my $ret = {};
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foreach my $m (keys %$trunks) {
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next unless $m and exists $ports->{$m} and defined $ports->{$m};
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my $skip = 0;
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while (my $s = unpack("x${skip}n2", $trunks->{$m})) {
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next unless $s and exists $ports->{$s} and defined $ports->{$s};
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$ret->{ $ports->{$s} } = $ports->{$m};
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$skip += 2;
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}
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